The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Serializer/deserializer (SERDES) devices are commonly used where systems communicate with each other over a communications channel using serial bitstreams. In particular, SERDES devices are used for systems that internally handle multi-bit data words over parallel busses. Each SERDES device typically includes a serializer that converts the data words to a serial bitstream before transmitting the bitstream over the channel. Each SERDES also typically includes a deserializer that converts a serial bitstream received from the channel to a plurality of data words.
FIG. 1 illustrates a conventional network device 10 including a medium access controller (MAC) module 12 with a Gigabit MAC 14 and a physical coding sublayer (PCS) module 16. An output of the MAC module 12 is input to a first SERDES 20, which provides a serial link at a fixed data rate. A second SERDES 22 communicates with the first SERDES 20 and is connected to a PCS module 26 of a physical layer (PHY) module 28 that also includes a PHY 30. The MAC module 12 communicates with higher level layers. The PHY 30 communicates with a medium 34. In one example, the PCS module 16 performs 8/10 bit encoding as specified by IEEE 802.3, which is incorporated herein by reference. Alternative examples include use of another suitable PCS coding. A serial management interface 36 provides control information between the MAC module 12 and the PHY module 28.